In recent years, as one of next-generation nonvolatile semiconductor memories, there is a magnetic random access memory (MRAM). The MRAM comprises an MTJ (Magnetic Tunnel Junction) element as a memory element, and the MTJ element has a stacked structure including a reference layer having an invariable spin direction, a recording layer having a spin direction that is variable according to, e.g., a write current, and a barrier layer provided between the reference layer and the recording layer. The MTJ element has low resistance when the spin directions of the reference layer and the recording layer are parallel to each other or has high resistance when these directions are anti-parallel, and it stores 1-bit data (data “0” and “1”) by utilizing a difference in current produced by a difference between these electrical resistances.
In such an MRAM, embedded use by mixing with other types of memory products is expected, and a reduction in chip size (layout) is desired in view of an increase in speed or a reduction in size of an entire system. On the other hand, when a layout is reduced, crosstalk (a current leak) between wiring lines is induced in a cell array section and a peripheral circuit section, and a manufacturing process having a small variation in transistor size is required to reduce a current leak.
The MRAM manufacturing process includes a process of flattening an upper surface of the MTJ element. At this time, since a covering rate of the MTJ element with respect to the cell array section and the peripheral circuit section is very low, there is a problem that processing with higher flatness is difficult. Low flatness of the MTJ element leads to a problem that deterioration of contact properties and a current leak between adjacent transistors are induced when an upper electrode or an upper wiring layer is formed on the MTJ element.